Power-on reset signal generator for semiconductor device

ABSTRACT

A power-on-reset signal is generated at a proper timing according to an object to which the power-on-reset signal is sent. A POR signal generating circuit for generating the power-on-reset signal is caused to operate with the voltage of an internal voltage generating circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device comprising asemiconductor chip on which an internal voltage generating circuit isprovided, and more particularly to a semiconductor device comprising areset signal generating circuit for generating a power-on-reset signal(hereinafter referred to as a POR signal) used for resetting an internalcircuit thereof when a power source is turned ON or for keeping circuitoperation halted until an internal potential is stabilized in order toprevent the unstable state from occurring when the power source isturned ON.

2. Description of the Background Art

In some cases, the semiconductor device has a structure in which theinternal circuit is reset when the power source is turned ON or thecircuit operation is kept halted until the internal potential isstabilized by using the POR signal in order to prevent the unstablestate from occurring when the power source is turned ON.

FIG. 25 is a block diagram showing the structure of a semiconductordevice which comprises a conventional POR signal generating circuit forgenerating a POR signal. In FIG. 25, reference numeral 1 designates asemiconductor chip, 2 designates a power input terminal provided on thesemiconductor chip 1 for receiving an external voltage ExVdd given fromthe outside of the semiconductor chip 1, 3 designates an internalcircuit provided in the semiconductor chip 1, 4 designates an internalvoltage generating circuit for supplying an internal voltage intVdd tothe internal circuit 3, and 5 designates a POR signal generating circuitfor generating a POR signal to be sent to the internal circuit 3 basedon the external voltage ExVdd.

FIG. 26 is a circuit diagram showing the structure of a POR circuit. InFIG. 26, reference numeral 6 designates an N channel MOS transistorhaving a gate to which the external voltage ExVdd is given, a drain towhich the external voltage ExVdd is given, and a source, 7 designates acapacitor having a first end connected to the source of the transistor 6and a second end connected to a ground potential point GND, 8 designatesan N channel MOS transistor having a gate to which the external voltageExVdd is given, a drain to which the external voltage ExVdd is given,and a source, 9 designates an N channel MOS transistor having a drainconnected to the source of the transistor 8, a source connected to theground potential point GND, and a gate connected to the first end of thecapacitor 7, 10 designates an inverter having an input terminalconnected to the drain of the transistor 9 and an output terminal forinverting and outputting the logic of a signal input to the inputterminal, and 11 designates an inverter having an input terminalconnected to the output terminal of the inverter 10 and an outputterminal for inverting and outputting the logic of a signal input to theinput terminal.

A pulse signal is output as the POR signal from the conventional PORsignal generating circuit. The pulse width of the POR signal isdetermined by the charging time of the capacitor 7 because theconventional POR signal generating circuit has the above structure.However, the conventional POR signal generating circuit has problemsthat the POR signal is generated depending on the rise speed of anexternal power source before the internal voltage generating circuitfully operates and that the POR signal is generated by the change of theexternal voltage.

It is preferred that POR signals outputted on different timings aregenerated depending on a circuit structure in some cases, for example,in the case where a plurality of internal voltage generating circuitsare provided on the semiconductor chip and the internal voltages havedifferent generation timings. In the case of a DRAM, a plurality ofpotentials such as a substrate potential Vbb, a cell plate potential Vcpand the like are necessary. According to the semiconductor chip in whichthe external voltage ExVdd is dropped inside and the internal voltageintVdd is used, the cell plate potential Vcp is often generated by theinternal voltage intVdd when the ground potential GND acts as areference in consideration of the stability of the potential. A couplingcapacity between a cell plate and a substrate is big. Consequently, thefloating of the substrate potential Vbb may be caused by the couplingcapacity when the cell plate potential Vcp rises. In order to preventthe floating, it is preferred that the substrate potential Vbb is keptfixed to the ground potential GND until the cell plate potential Vcprises.

However, the POR signal generating circuit according to the prior arthas the following problems. More specifically, the POR signal isgenerated by only the external voltage. For this reason, it is hard togenerate signals which rise (or fall) at different timings, that is, ata comparatively early timing as the POR signal of the internal voltagegenerating circuit, and a signal which rises (or falls) after the cellplate potential Vcp is stabilized, that is, at a comparatively latetiming as the POR signal of the internal voltage generating circuit usedfor setting the substrate potential Vbb.

SUMMARY OF THE INVENTION

A first aspect of the present invention is directed to a semiconductordevice comprising an internal circuit provided in a semiconductor chip,a power input terminal provided on the semiconductor chip for receivingan external voltage given from the outside of the semiconductor chip, aninternal voltage generating circuit provided in the semiconductor chipand connected to the power input terminal for generating an internalvoltage to be supplied to the internal circuit based on the externalvoltage, and a first reset signal generating circuit provided in thesemiconductor chip for generating a first reset signal in response tothe internal voltage to reset the internal circuit or to keep circuitoperation halted until a predetermined state is obtained.

A second aspect of the present invention is directed to thesemiconductor device according to the first aspect of the presentinvention, wherein the internal circuit comprises a first circuit unitfor operating with the internal voltage, and a second circuit unit foroperating with the external voltage, the first and second circuit unitsbeing reset or circuit operation being kept halted until a predeterminedstate is obtained with the first reset signal.

A third aspect of the present invention is directed to the semiconductordevice according to the first aspect of the present invention, furthercomprising a second reset signal generating circuit provided in thesemiconductor chip for generating a second reset signal in response tothe external voltage to reset the internal circuit or to keep circuitoperation halted until a predetermined state is obtained, wherein theinternal circuit comprises a first circuit unit for operating with theinternal voltage, and a second circuit unit for operating with theexternal voltage, the first circuit unit being reset or circuitoperation being kept halted until a predetermined state is obtained withthe first reset signal, and the second circuit unit being reset orcircuit operation being kept halted until a predetermined state isobtained with the second reset signal.

A fourth aspect of the present invention is directed to thesemiconductor device according to the first aspect of the presentinvention, wherein the internal voltage generating circuit comprisesfirst and second internal voltage generating circuits for respectivelygenerating first and second internal voltages which are different fromeach other, the first reset signal generating circuit comprises a secondreset signal generating circuit provided in the semiconductor chip forgenerating a second reset signal in response to the first internalvoltage to reset the internal circuit or to keep circuit operationhalted until a predetermined state is obtained, and a third reset signalgenerating circuit provided in the semiconductor chip for generating athird reset signal in response to the second internal voltage to resetthe internal circuit or to keep circuit operation halted until apredetermined state is obtained, wherein the internal circuit comprisesa first circuit unit for operating with the first internal voltage, anda second circuit unit for operating with the second internal voltage,the first circuit unit being reset or circuit operation being kepthalted until a predetermined state is obtained with the second resetsignal, and the second circuit unit being reset or circuit operationbeing kept halted until a predetermined state is obtained with the thirdreset signal.

A fifth aspect of the present invention is directed to the semiconductordevice according to the first aspect of the present invention, whereinthe internal voltage generating circuit comprises first and secondinternal voltage generating circuits for generating first and secondinternal voltages which are different from each other, and the firstreset signal generating circuit generates the first reset signalaccording to the first internal voltage, wherein the internal circuitcomprises a first circuit unit for operating with the first internalvoltage, and a second circuit unit for operating with the secondinternal voltage, the first and second circuit units being reset orcircuit operation being kept halted until a predetermined state isobtained with the first reset signal.

A sixth aspect of the present invention is directed to the semiconductordevice according to any of the first to fifth aspects of the presentinvention, further comprising an internal power source reset signalgenerating circuit provided in the semiconductor chip for generating aninternal power source reset signal in response to the external voltage,the internal voltage generating circuit being reset or circuit operationbeing kept halted until a predetermined state is obtained with theinternal power source reset signal.

A seventh aspect of the present invention is directed to thesemiconductor device according to the first aspect of the presentinvention, further comprising a lower rank internal voltage generatingcircuit provided in the semiconductor chip for generating a lower rankinternal voltage used in an internal circuit based on an internalvoltage given from the internal voltage generating circuit, and a lowerrank reset signal generating circuit provided in the semiconductor chipfor generating a lower rank reset signal in response to the lower rankinternal voltage to reset the internal circuit or keep circuit operationhalted until a predetermined state is obtained.

An eighth aspect of the present invention is directed to thesemiconductor device according to any of the first to seventh aspects ofthe present invention, wherein the first reset signal generating circuitgenerates the first reset signal in response to the external voltage andthe internal voltage.

A ninth aspect of the present invention is directed to the semiconductordevice according to any of the first to seventh aspects of the presentinvention, wherein the internal voltage generating circuit comprisesfirst and second internal voltage generating circuits for generatingfirst and second internal voltages which are different from each other,the first reset signal generating circuit generating the first resetsignal which takes the shape of a pulse having leading and trailingedges according to the first and second internal voltages.

A tenth aspect of the present invention is directed to the semiconductordevice according to any of the first to ninth aspects of the presentinvention, wherein the first reset signal generating circuit comprisescomparing means for comparing the voltages of predetermined two nodes inthe internal voltage generating circuit, and reset signal generatingmeans for generating the first reset signal in response to the resultsof comparison obtained by the comparing means.

An eleventh aspect of the present invention is directed to thesemiconductor device according to any of the first to tenth aspects ofthe present invention, wherein the first reset signal generating circuitgenerates the first reset signal in response to a reference voltagegenerated in the internal voltage generating circuit or a voltage outputfrom a circuit having the same structure as that of the internal voltagegenerating circuit in which the reference voltage is generated.

A twelfth aspect of the present invention is directed to thesemiconductor device according to the tenth aspect of the presentinvention, wherein the comparing means comprises a first transistor of afirst conductivity type having a first current electrode connected to afirst power potential point, a control electrode connected to a firstinput terminal, and a second current electrode, a second transistor ofthe first conductivity type having a control electrode connected to thefirst input terminal, a first current electrode connected to the secondcurrent electrode of the first transistor, and a second currentelectrode, a third transistor of the first conductivity type having afirst current electrode connected to the second current electrode of thefirst transistor, a control electrode connected to a second inputterminal, and a second current electrode, a fourth transistor of asecond conductivity type having a first current electrode connected to asecond power potential point, a control electrode, and a second currentelectrode connected to the second current electrode of the firsttransistor, a fifth transistor of the second conductivity type having afirst current electrode connected to the second power potential point, acontrol electrode connected to the second current electrode of thefourth transistor, a control electrode, and a second current electrodeconnected to the second current electrode of the second transistor, asixth transistor of the second conductivity type having a first currentelectrode connected to the control electrode of the fourth transistor, asecond current electrode connected to the control electrode of the fifthtransistor, and a control electrode, a seventh transistor of the secondconductivity type having a first current electrode connected to thecontrol electrode of the fourth transistor, a control electrode, and asecond current electrode connected to the second current electrode ofthe third transistor, a first inverter having an input terminalconnected to the second current electrode of the third transistor, andan output terminal, a second inverter having an input terminal connectedto the output terminal of the first inverter, and an output terminalconnected to the control electrode of the sixth transistor, and a thirdinverter having an input terminal connected to the output terminal ofthe second inverter, and an output terminal connected to the controlelectrode of the seventh transistor, wherein the results of comparisonare output from the output terminal of the second inverter

A thirteenth aspect of the present invention is directed to a comparingcircuit comprising a first transistor of a first conductivity typehaving a first current electrode connected to a first power potentialpoint, a control electrode connected to a first input terminal, and asecond current electrode, a second transistor of the first conductivitytype having a control electrode connected to the first input terminal, afirst current electrode connected to the second current electrode of thefirst transistor, and a second current electrode, a third transistor ofthe first conductivity type having a first current electrode connectedto the second current electrode of the first transistor, a controlelectrode connected to a second input terminal, and a second currentelectrode, a fourth transistor of a second conductivity type having afirst current electrode connected to a second power potential point, acontrol electrode, and a second current electrode connected to thesecond current electrode of the first transistor, a fifth transistor ofthe second conductivity type having a first current electrode connectedto the second power potential point, a control electrode connected tothe second current electrode of the fourth transistor, and a secondcurrent electrode connected to the second current electrode of thesecond transistor, a sixth transistor of the second conductivity typehaving a first current electrode connected to the control electrode ofthe fourth transistor, a second current electrode connected to thecontrol electrode of the fifth transistor, and a control electrode, aseventh transistor of the second conductivity type having a firstcurrent electrode connected to the control electrode of the fourthtransistor, a control electrode, and a second current electrodeconnected to the second current electrode of the third transistor, afirst inverter having an input terminal connected to the second currentelectrode of the third transistor, and an output terminal, a secondinverter having an input terminal connected to the output terminal ofthe first inverter, and an output terminal connected to the controlelectrode of the sixth transistor, and a third inverter having an inputterminal connected to the output terminal of the second inverter, and anoutput terminal connected to the control electrode of the seventhtransistor, wherein the results of comparison are output from the outputterminal of the second inverter.

In order to solve the above problems, it is an object of the presentinvention to generate a stable POR signal which is hardly influenced bythe change of an external voltage.

It is another object of the present invention to provide a semiconductordevice which can perform resetting or halt circuit operations ofcircuits at different timings.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the structure of a semiconductordevice according to a first embodiment of the present invention;

FIG. 2 is a block diagram showing the structure of a semiconductordevice according to a second embodiment of the present invention;

FIG. 3 is a block diagram showing the structure of a semiconductordevice according to a third embodiment of the present invention;

FIG. 4 is a block diagram showing the structure of a semiconductordevice according to a fourth embodiment of the present invention;

FIG. 5 is a block diagram showing the structure of a semiconductordevice according to a fifth embodiment of the present invention;

FIG. 6 is a block diagram showing the structure of a semiconductordevice according to a sixth embodiment of the present invention;

FIG. 7 is a block diagram showing the structure of a semiconductordevice according to a seventh embodiment of the present invention;

FIG. 8 is a block diagram showing the structure of a semiconductordevice according to an eighth embodiment of the present invention;

FIG. 9 is a block diagram showing the structure of a semiconductordevice according to a ninth embodiment of the present invention;

FIG. 10 is a block diagram showing the structure of a semiconductordevice according to a tenth embodiment of the present invention;

FIG. 11 is a circuit diagram showing a first mode of the structure of aPOR signal generating circuit;

FIG. 12 is a wave form chart showing the operation of the circuit shownin FIG. 11;

FIG. 13 is a circuit diagram showing means for forming a substratepotential Vbb on a ground potential GND;

FIG. 14 is a circuit diagram showing a second mode of the structure ofthe POR signal generating circuit;

FIG. 15 is a wave form chart showing the operation of the circuit shownin FIG. 14;

FIG. 16 is a circuit diagram showing a third mode of structure of theinternal voltage generating circuit and POR signal generating circuit;

FIG. 17 is a wave form chart showing the operation of the circuit shownin FIG. 16;

FIG. 18 is a circuit diagram showing the structure of a comparingcircuit;

FIG. 19 is a circuit diagram showing the structure of a pulse generator;

FIG. 20 is a circuit diagram showing another mode of the structure ofthe comparing circuit;

FIG. 21 is a wave form chart showing the operation of the circuit shownin FIG. 20;

FIG. 22 is a block diagram showing the structure of a semiconductordevice according to an eleventh embodiment of the present invention;

FIG. 23 is a block diagram showing the structure of a semiconductordevice according to a twelfth embodiment of the present invention;

FIG. 24 is a circuit diagram showing the structure of a POR signalgenerating circuit shown in FIG. 22;

FIG. 25 is a block diagram showing the structure of a conventionalsemiconductor device; and

FIG. 26 is a circuit diagram showing the structure of a conventional PORsignal generating circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(First Embodiment)

FIG. 1 is a block diagram showing the structure of a semiconductordevice according to a first embodiment of the present invention. In FIG.1, reference numeral 1 designates a semiconductor chip, 2 designates apower input terminal provided on the semiconductor chip 1 for receivingan external voltage ExVdd given from the outside of the semiconductorchip 1, 3 designates an internal circuit provided in the semiconductorchip 1, 4 designates an internal voltage generating circuit forsupplying an internal voltage intVdd to the internal circuit 3, and 12designates a POR signal generating circuit for generating a POR signalto be sent to the internal circuit 3 based on the internal voltageintVdd.

The POR signal is generated based on the internal voltage intVdd.Consequently, the POR signal can be generated after the internal voltageintVdd is stabilized. In addition, the malfunction of the POR signalgenerating circuit caused by the fluctuation of the external voltageExVdd can also be reduced.

A method for causing the POR signal generating circuit to operate withthe internal voltage intVdd and a method for detecting the change of theinternal voltage intVdd are worked out as a method for generating thePOR signal based on the internal voltage intVdd. The structures forimplementing these methods will be described below.

FIG. 11 is a circuit diagram showing the structure of the POR signalgenerating circuit 12 in FIG. 1. In FIG. 11, reference numeral 6Adesignates an N channel MOS transistor having a gate to which aninternal voltage intVdd is given, a drain to which the internal voltageintVdd is given, and a source, 7 designates a capacitor having a firstend connected to the source of the transistor 6A and a second endconnected to a ground potential point GND, 8A designates an N channelMOS transistor having a gate to which the internal voltage intVdd isgiven, a drain to which the internal voltage intVdd is given, and asource, 9 designates an N channel MOS transistor having a drainconnected to the source of the transistor 8A, a source connected to theground potential point GND, and a gate connected to the first end of thecapacitor 7, 10A designates an inverter having an input terminalconnected to the drain of the transistor 9 and an output terminal forinverting and outputting the logic of a signal input to the inputterminal, and 11A designates an inverter having an input terminalconnected to the output terminal of the inverter 10 and an outputterminal for inverting and outputting the logic of a signal input to theinput terminal. The inverters 10A and 11A operate on receipt of thesupply of the internal voltage intVdd.

FIG. 12 is a wave form chart showing a difference in operation betweenthe POR signal generating circuit 5 in FIG. 25 and the POR signalgenerating circuit 12 in FIG. 11. As shown in FIG. 12, the externalvoltage ExVdd is higher than the internal voltage intVdd. As a matter ofcourse, it is apparent that the external voltage ExVdd rises earlierthan the internal voltage intVdd on an origin where a power source isturned ON. Referring to the conventional POR signal generating circuit 5which operates with the external voltage ExVdd shown in FIG. 25, the PORsignal (indicated at ExVdd system POR in FIG. 12) output from theconventional POR signal generating circuit 5 sometimes rises earlierthan the internal voltage intVdd depending on the setting of thecapacitor 7 as shown in FIG. 12. On the other hand, the POR signaloutput from the POR signal generating circuit 12 for operating onreceipt of the internal voltage intVdd (indicated at intVdd system PORin FIG. 12) always rises later than the internal voltage intVdd. Forthis reason, the internal circuit 3 is not reset, or is not started bythe internal voltage generating circuit 4 in the unstable state so thatthe POR signal can be generated with the internal voltage intVdd stableeasily. Furthermore, the POR signal generating circuit 12 is caused tooperate with the internal voltage intVdd. Consequently, even if theexternal voltage ExVdd fluctuates, the POR signal is not generated whilethe internal voltage intVdd is in the stable state. Thus, a malfunctioncan be prevented from occurring.

A second mode of the POR signal generating circuit 12 will be describedbelow with reference to FIGS. 14 and 15. The POR signal generatingcircuit shown in FIG. 14 does not take the generation timing of the PORsignal with the time constant of the capacitor but detects that areference voltage is generated by a reference voltage generating circuitprovided in the internal voltage generating circuit or POR signalgenerating circuit and generates the POR signal.

In FIG. 14, reference numeral 30 designates a reference voltagegenerating circuit for generating a reference voltage on receipt of theexternal voltage ExVdd, 31 designates a driver connected to thereference voltage generating circuit 30 for outputting a signal by thegeneration of the reference voltage, and 32 designates a signalgenerating unit for generating the POR signal from the output of thedriver 31.

The reference voltage generating circuit 30 comprises a resistor 33having a first end connected to a ground potential point GND, and asecond end; an N channel MOS transistor 34 having a source connected tothe second end of the resistor 33, a gate, and a drain; a P channel MOStransistor 35 having a source to which the external voltage Vdd isgiven, a drain connected to the drain of the N channel MOS transistor34, and a gate connected to the drain of the N channel MOS transistor34; an N channel MOS transistor 36 having a gate connected to the gateof the N channel MOS transistor 34, a source to which the groundpotential point GND is given, and a drain connected to the gate of the Nchannel MOS transistor 34; and a P channel MOS transistor 37 having adrain connected to the drain of the N channel MOS transistor 36, a gateconnected to the gate of the P channel MOS transistor 35, and a sourceto which the external voltage ExVdd is given.

The driver 31 comprises a P channel MOS transistor 38 having a source towhich the external voltage ExVdd is given, a gate connected to the gateof the P channel MOS transistor 35, and a drain connected to a node B,and a resistor 39 having a first end connected to the ground potentialpoint GND and a second end connected to the node B.

The signal generating unit 32 comprises an N channel MOS transistor 40having a source connected to the ground potential point GND, a gateconnected to the node B, and a drain; an N channel MOS transistor 41having a source connected to the ground potential point GND, a gate, anda drain connected to a node C; an inverter 42 which has an inputterminal connected to the gate of the N channel MOS transistor 40, andan output terminal connected to the gate of the N channel MOS transistor41, and delays a signal; a P channel MOS transistor 43 having a sourceto which the external voltage ExVdd is given, a drain connected to thedrain of the N channel MOS transistor 40, and a gate connected to thenode C; a P channel MOS transistor 44 having a drain connected to thenode C, a gate connected to the drain of the P channel MOS transistor43, and a source to which the external voltage ExVdd is given; and aninverter 45 having an input terminal connected to the node C, and anoutput terminal for inverting and outputting a signal input to the inputterminal.

The operation of the POR signal generating circuit shown in FIG. 14 willbe described below with reference to FIG. 15. When the external voltageExVdd is raised and exceeds the thresholds of the P channel MOStransistors 35 and 37, a current starts to flow to the reference voltagegenerating circuit 30. When the current flows to the reference voltagegenerating circuit 30, the voltage of a node A1 is raised. When theexternal voltage ExVdd is then raised and becomes higher than thevoltage of the node A1 by the threshold of the P channel MOS transistor,the voltage of the node B starts to be raised. When the voltage of thenode B exceeds the threshold of the inverter 42 on the next stage, thePOR signal is generated. By using the same structure as that of theinternal voltage generating circuit 4 or the structure of the internalvoltage generating circuit 4 for the reference voltage generatingcircuit 30, the POR signal can be generated after a power potential onthe inside of the semiconductor chip 1 is stabilized.

A third mode of the POR signal generating circuit 12 will be describedbelow with reference to FIGS. 16 to 19. FIG. 16 is a block diagramshowing the structures of the internal voltage generating circuit andPOR signal generating circuit. In FIG. 16, reference numeral 60designates a comparing circuit for comparing the predetermined nodevoltage of the reference voltage generating circuit 30 with the outputvoltage of the driver 31, and 70 designates a pulse generator forgenerating and outputting a pulse signal according to the timing of theoutput of the comparing circuit 60.

As shown in FIG. 18, the comparing circuit 60 comprises an N channel MOStransistor 61 having a gate connected to the node B, a source connectedto a ground potential point GND, and a drain; an N channel MOStransistor 62 having a gate connected to a node A2, a source connectedto the ground potential point GND, and a drain; a P channel MOStransistor 63 having a drain connected to the drain of the N channel MOStransistor 61, a gate connected to the drain of the N channel MOStransistor 61, and a source to which the external voltage ExVdd isgiven; a P channel MOS transistor 64 having a drain connected to thedrain of the N channel MOS transistor 62, a gate connected to the gateof the P channel MOS transistor 63, and a source to which the externalvoltage ExVdd is given; an inverter 65 having an input terminalconnected to the drain of the P channel MOS transistor 64, and an outputterminal for inverting and outputting a signal received by the inputterminal; and an inverter 66 having an input terminal connected to theoutput terminal of the inverter 65, and an output terminal for invertingand outputting a signal received by the input terminal.

As shown in FIG. 19, the pulse generator 70 comprises an inverter 71having an input terminal for receiving the output of the inverter 66,and an output terminal for inverting and outputting a signal received bythe input terminal; an inverter 72 having an input terminal connected tothe output terminal of the inverter 71, and an output terminal forinverting and outputting a signal received by the input terminal; aninverter 73 having an input terminal connected to the output terminal ofthe inverter 72, and an output terminal for inverting and outputting asignal received by the input terminal; and an NAND gate 74 having afirst input terminal connected to the node C, a second input terminalconnected to the inverter 73, and an output terminal for outputting ANDof signals received by the first and second input terminals.

The operation of the internal voltage generating circuit and POR signalgenerating circuit shown in FIG. 16 will be described below withreference to FIG. 17. The comparing circuit 60 for comparing the voltageof the node A2 with that of the node B outputs a high level when thevoltage of the node B is higher than that of the node A2. Referring tothe circuit shown in FIG. 18, when the voltage of the node B is higherthan that of the node A2, the N channel MOS transistor 61 is turned ONmore strongly than the N channel MOS transistor 62. Consequently, acurrent flows to the input terminal of the inverter 65 by means of acurrent mirror circuit formed by the P channel MOS transistor 63 and theP channel MOS transistor 64 so that the voltage of the output terminalof the inverter 65 is set to a low level. For this reason, the voltageof the output terminal of the inverter 66 is set to a high level.

When the comparing circuit 60 outputs the high level, the pulsegenerator 70 generates a pulse signal. Referring to the circuit shown inFIG. 19, the first input terminal has the low level while the output ofthe comparing circuit 60 has the low level. Consequently, the secondinput terminal connected to the inverter 73 has the high level and theNAND gate 74 outputs the low level. When the output of the comparingcircuit 60 is changed from the low level to the high level, the secondinput terminal of the NAND gate 74 is set to the low level later thanthe first input terminal of the NAND gate 74 is set to the high level bytransmission on the inverters 71 to 73. Consequently, a pulse signalhaving a pulse width which is equivalent to the delay time is output.

A fourth mode of the POR signal generating circuit 12 will be describedbelow with reference to FIGS. 20 and 21. FIG. 20 is a circuit diagramshowing another mode of the comparing circuit 60 shown in FIG. 16. InFIG. 16, reference numeral 81 designates an N channel MOS transistorhaving a source connected to the ground potential point GND, a gateconnected to the node B, and a drain, 82 designates an N channel MOStransistor having a source connected to the drain of the N channel MOStransistor 81, a gate connected to the node B, and a drain connected toa node E, 83 designates an N channel MOS transistor having a sourceconnected to the drain of the N channel MOS transistor 81, a gateconnected to the node A2, and a drain connected to a node D, 84designates a P channel MOS transistor having a drain connected to thenode E, a source to which the external voltage ExVdd is given, and agate connected to a node G, 85 designates a P channel MOS transistorhaving a drain connected to the node D, a source to which the externalvoltage ExVdd is given, and a gate connected to the node E, 86designates a transfer gate having a first current electrode connected tothe node G, a second current electrode connected to the gate of the Pchannel MOS transistor 85, and a gate, 87 designates a transfer gatehaving a first current electrode connected to the node D, a secondcurrent electrode connected to the node G, and a gate, 88 designates aninverter having an input terminal connected to the node D, and an outputterminal for inverting and outputting the signal of the node D, 89designates an inverter having an input terminal connected to the outputterminal of the inverter 88, and an output terminal connected to thegate of the transfer gate 86, and 90 designates an inverter having aninput terminal connected to the output terminal of the inverter 89, andan output terminal connected to the gate of the transfer gate 87.

The operation of the comparing circuit shown in FIG. 20 will bedescribed below with reference to FIG. 21. Since the output terminal ofthe inverter 89 has a low level, the transfer gate 86 is ON. Since thenode D also has the low level, the transfer gate 87 is ON. Immediatelyafter a power source is turned ON, the nodes D, E and G are set to aground potential (0 V potential). For this reason, the P channel MOStransistors 84 and 85 are ON.

When the external voltage ExVdd is raised, the voltages of the nodes Dand E are raised because the P channel MOS transistors 84 and 85 are ON.If the voltages of the nodes D and E exceed the threshold voltages ofthe P channel MOS transistors 84 and 85, the P channel MOS transistors84 and 85 are turned OFF so that a rise in voltage of the nodes D and Eis almost stopped. The node D is not set to the high level. For thisreason, the node C is set to the low level and a node F is set to thehigh level. The node C has the ground potential, and the voltage of thenode F is raised with the external voltage ExVdd.

When the voltage of the node B is raised and becomes higher than that ofthe node A2, the voltage of the node D is raised and that of the node Eis dropped. When the voltage of the node D is raised and exceeds thethreshold voltage of the inverter 88, the inverter 88 outputs the lowlevel so that the output of the inverter 89 is set to the high level.Consequently, the transfer gate 86 is turned OFF and the output of theinverter 90 is set to the low level so that the transfer gate 87 isturned ON. Consequently, the P channel MOS transistor 84 is turned OFFand the P channel MOS transistor 85 is turned ON. However, since thegate voltage of the N channel MOS transistor 83 is low, a small amountof current flow is enough. Consequently, a through current can bereduced.

Each POR signal generating circuit described above can be applied to PORsignal generating circuits used in second to tenth embodiments.

(Second Embodiment)

FIG. 2 is a block diagram showing the structure of a semiconductordevice according to a second embodiment of the present invention. InFIG. 2, reference numeral 5 designates a POR signal generating circuitfor generating a POR signal to be given to an internal circuit 3 basedon an external voltage ExVdd, and the same reference numbers designatethe same units as in FIG. 1. The internal circuit 3 comprises a firstcircuit unit 3a for operating on receipt of an internal voltage intVdd,and a second circuit unit 3c for operating on receipt of the externalvoltage ExVdd. For example, the first circuit unit 3a is reset or thestart of operation thereof is delayed by a POR signal generating circuit12, and the second circuit unit 3c is reset or the start of operationthereof is delayed by the POR signal generating circuit 5.

The first and second circuit units 3a and 3c are controlled by the PORsignals of the POR signal generating circuits 5 and 12 which aredifferent from each other. Consequently, the operation of the first andsecond circuit units 3a and 3c can be started at proper timings at whichthey are stabilized.

(Third Embodiment)

FIG. 3 is a block diagram showing the structure of a semiconductordevice according to a third embodiment of the present invention. In FIG.3, the same reference numbers designate the same units as in FIG. 2. Thesemiconductor device shown in FIG. 3 differs from the semiconductordevice shown in FIG. 2 in that the second circuit unit 3c of thesemiconductor device shown in FIG. 2 receives the POR signal of the PORsignal generating circuit 5 and a second circuit unit 3b of thesemiconductor device shown in FIG. 3 receives the POR signal of a PORsignal generating circuit 12. If it is sufficient that the operation ofthe second circuit unit 3b is started after an external voltage ExVdd orinternal voltage intVdd is stabilized, the POR signal is sent to theinternal circuit 3 and the second circuit unit 3b by the POR signalgenerating circuit 12 so that the POR signal generating circuit 5 shownin FIG. 2 can be omitted.

(Fourth Embodiment)

FIG. 4 is a block diagram showing the structure of a semiconductordevice according to a fourth embodiment of the present invention. InFIG. 4, reference numeral 4A designates a first internal voltagegenerating circuit for supplying a first internal voltage intVdd1 to aninternal circuit 3, 4B designates a second internal voltage generatingcircuit for supplying a second internal voltage intVdd2 to the internalcircuit 3, 12A designates a first POR signal generating circuit forgenerating a first POR signal according to the first internal voltageintVdd1 of the first internal voltage generating circuit 4A, and 12Bdesignates a second POR signal generating circuit for generating asecond POR signal according to the second internal voltage intVdd2 ofthe second internal voltage generating circuit 4B, and the samereference numbers designate the same units as in FIG. 1. Thesemiconductor device shown in FIG. 4 differs from the semiconductordevice shown in FIG. 1 in that the internal circuit 3 comprises a firstcircuit unit 3a and a fourth circuit unit 3d for operating according tothe internal voltages intVdd1 and intVdd2 which are different from eachother. In the case where a plurality of internal voltage generatingcircuits 4A and 4B are provided, POR signals corresponding to respectiveinternal voltage generating circuits are sent to the first and fourthcircuit units 3a and 3d to which respective internal voltages intVdd1and intVdd2 are given so that power-on-reset can be performed moreprecisely.

(Fifth Embodiment)

FIG. 5 is a block diagram showing the structure of a semiconductordevice according to a fifth embodiment of the present invention. In FIG.5, the same reference numbers designate the same units as in FIG. 4. Thesemiconductor device shown in FIG. 5 differs from the semiconductordevice shown in FIG. 4 in that a fifth circuit unit 3e and a sixthcircuit unit 3f for operating with an external voltage ExVdd areprovided in an internal circuit 3. The fifth circuit unit 3e is reset bythe POR signal of a first POR signal generating circuit 12A, and thesixth circuit unit 3f is reset by the POR signal of a second POR signalgenerating circuit 12B. The circuit units which operate with the sameexternal voltage ExVdd can be reset at different timings so that properpower-on-reset can be performed easily.

(Sixth Embodiment)

FIG. 6 is a block diagram showing the structure of a semiconductordevice according to a sixth embodiment of the present invention. In FIG.6, the same reference numbers designate the same units as in FIG. 4. Thesemiconductor device shown in FIG. 6 differs from the semiconductordevice shown in FIG. 4 in that a seventh circuit unit 3g for receivingan internal voltage intVdd from a second internal voltage generatingcircuit 4B is reset by a first POR signal generating circuit 12A. Asshown in FIG. 6, if it is sufficient that the seventh circuit unit 3goperates after the output of a first internal voltage generating circuit4A is stabilized, the seventh circuit unit 3g can be reset by the firstPOR signal generating circuit 12A with a second POR signal generatingcircuit 12B omitted.

(Seventh Embodiment)

FIG. 7 is a block diagram showing the structure of a semiconductordevice according to a seventh embodiment of the present invention. InFIG. 7, reference numeral 5 designates a POR signal generating circuitfor generating a POR signal to be sent to an internal circuit 3 based onan external voltage ExVdd, 4C designates an internal voltage generatingcircuit which is reset by the POR signal output from the POR signalgenerating circuit 5, and the same reference numbers designate the sameunits as in FIG. 1.

In the case of a DRAM, a plurality of potentials such as a substratepotential Vbb, a cell plate potential Vcp and the like are necessary.According to a semiconductor chip in which the external voltage ExVdd isdropped inside and an internal voltage intVdd generated by the droppedexternal voltage ExVdd is used, the internal voltage generating circuit4C for giving the cell plate potential Vcp generated by the internalvoltage intVdd in which a ground potential GND acts as a reference isreset by the POR signal generating circuit 5, and the substratepotential Vbb is kept fixed to the ground potential GND until the cellplate potential Vcp rises by the POR signal output from a POR signalgenerating circuit 12 so that the floating of the substrate voltage Vbbcan be prevented from occurring. As shown in FIG. 13, a line forsupplying the substrate potential Vbb may be connected to a line forsupplying the ground potential GND in a transistor 22 having a gate forreceiving an internal voltage intVdd system POR signal, or the operationof a circuit itself for giving the substrate potential Vbb may becontrolled so as to fix the substrate potential Vbb to the groundpotential GND.

Thus, a plurality of POR signals can surely be generated at differenttimings so that power-on-reset can be performed properly.

(Eighth Embodiment)

FIG. 8 is a block diagram showing the structure of a semiconductordevice according to an eighth embodiment of the present invention. InFIG. 8, reference numeral 4C designates an internal voltage generatingcircuit on which power-on-reset is performed by a POR signal generatingcircuit 5, and the same reference numbers designate the same units as inFIG. 2. The semiconductor device shown in FIG. 8 differs from thesemiconductor device shown in FIG. 2 in that the internal voltagegenerating circuit 4 is different from the internal voltage generatingcircuit 4C. The same effects as in the seventh embodiment can beobtained.

(Ninth Embodiment)

FIG. 9 is a block diagram showing the structure of a semiconductordevice according to a ninth embodiment of the present invention. In FIG.9, reference numeral 4C designates an internal voltage generatingcircuit on which power-on-reset is performed by a POR signal generatingcircuit 5, and the same reference numbers designate the same units as inFIG. 3. The semiconductor device shown in FIG. 9 differs from thesemiconductor device shown in FIG. 3 in that the internal voltagegenerating circuit 4 is different from the internal voltage generatingcircuit 4C. The same effects as in the seventh embodiment can beobtained.

(Tenth Embodiment)

FIG. 10 is a block diagram showing the structure of a semiconductordevice according to a tenth embodiment of the present invention. In FIG.10, reference numeral 13 designates a second internal voltage generatingcircuit on which power-on-reset is performed by a POR signal generatingcircuit 12 on receipt of an internal voltage intVdd from a firstinternal voltage generating circuit 4, 14 designates a third internalvoltage generating circuit on which power-on-reset is performed by thePOR signal generating circuit 12 on receipt of the internal voltageintVdd from the first internal voltage generating circuit 4, 15designates a POR signal generating circuit for generating a POR signalon receipt of an internal voltage intVdd2 of the second internal voltagegenerating circuit 13, 16 designates a POR signal generating circuit forgenerating a POR signal on receipt of an internal voltage intVdd3 of thethird internal voltage generating circuit 14, 3h designates an eighthcircuit unit for receiving the second internal voltage intVdd2 from thesecond internal voltage generating circuit 13 and for receiving the PORsignal from the POR signal generating circuit 15, and 3i designates aninth circuit unit for receiving the third internal voltage intVdd3 fromthe third internal voltage generating circuit 14 and for receiving thePOR signal from the POR signal generating circuit 16,

Power-on-reset is performed on the second internal voltage generatingcircuit 13 and the third internal voltage generating circuit 14 by thePOR signal generating circuit 12 for outputting the POR signal based onthe internal voltage output from the first internal voltage generatingcircuit 4. Consequently, stable operation can be obtained irrespectiveof the change of an external voltage ExVdd.

The eighth and ninth circuit units 3h and 3i of the internal circuit 3are hardly influenced by the external voltage because they are generatedaccording to the internal voltages output from the second and thirdinternal voltage generating circuits 13 and 14. In addition,power-on-reset is performed after the internal voltage output from thefirst internal voltage generating circuit 4 is stabilized. Consequently,a malfunction can be restrained.

(Eleventh Embodiment)

FIG. 22 is a block diagram showing the structure of a semiconductordevice according to an eleventh embodiment of the present invention. InFIG. 22, 20 designates a POR signal generating circuit for generating aPOR signal according to an external voltage ExVdd and an internalvoltage intVdd output from an internal voltage generating circuit 4, andthe same reference numbers designate the same units as in FIG. 1. ThePOR signal generating circuit 20 determines a rise timing according tothe external voltage ExVdd and a fall time according to the internalvoltage intVdd so that a pulse signal is generated.

FIG. 24 shows an example of the structure of the POR signal generatingcircuit 20 shown in FIG. 22. In FIG. 24, reference numeral 6 designatesan N channel MOS transistor having a gate to which the internal voltageintVdd is given, a drain to which the internal voltage intVdd is given,and a source, 7 designates a capacitor having a first end connected tothe source of the transistor 6, and a second end connected to a groundpotential point GND, 8B designates an N channel MOS transistor having agate to which the external voltage ExVdd is given, a drain to which theexternal voltage ExVdd is given, and a source, 9 designates an N channelMOS transistor having a drain connected to the source of the transistor8B, a source connected to the ground potential point GND, and a gateconnected to the first end of the capacitor 7, 10 designates an inverterhaving an input terminal connected to the drain of the transistor 9, andan output terminal for inverting and outputting the logic of a signalinput to the input terminal, and 11 designates an inverter having aninput terminal connected to the output terminal of the inverter 10, andan output terminal for inverting and outputting the logic of a signalinput to the input terminal. The inverters 10 and 11 also operate onreceipt of the supply of the external voltage ExVdd.

Electric charges are stored in the capacitor 7 through the N channel MOStransistor 6 with a rise in internal voltage intVdd. Accordingly, thePOR signal rises at almost the same timing as that of a rise in intVddsystem POR shown in FIG. 12. When a current supplied to the N channelMOS transistor 9 through the N channel MOS transistor 8B is increasedand exceeds the threshold of the inverter 10, the output of the inverter10 is inverted and the output of the inverter 11 is set to a low level.The fall timing of the POR signal is almost the same as that of ExVddsystem POR shown in FIG. 12.

Thus, the rise and fall timings are based on the change of differentsupply voltages so that various kinds of POR signals can be obtained. Inaddition, it is easy to generate the POR signal corresponding to theinternal circuit which operates with a plurality of supply voltages.

(Twelfth Embodiment)

FIG. 23 is a block diagram showing the structure of a semiconductordevice according to a twelfth embodiment of the present invention. InFIG. 23, reference numeral 21 designates a POR signal generating circuitfor generating a POR signal according to internal voltage IntVdd1 andIntVdd2 output from an internal voltage generating circuit 4, and thesame reference numbers designate the same units as in FIG. 4. The PORsignal generating circuit 21 shown in FIG. 23 determines the rise andfall timings of the POR signal based on internal voltages supplied fromfirst and second internal voltage generating circuits 4A and 4B. Thesame effects as in the eleventh embodiment can be obtained.

While the invention has been described in detail, the foregoingdescription is in all aspects illustrative and not restrictive. It isunderstood that numerous other modifications and variations can bedevised without departing from the scope of the invention.

We claim:
 1. A semiconductor device comprising:a power input terminalprovided on a semiconductor chip for receiving an external voltageapplied from outside said semiconductor chip, a first internal circuitprovided on said semiconductor chip for operating with an internalvoltage, a second internal circuit provided on said semiconductor chipfor operating with said external voltage, an internal voltage generatingcircuit provided on said semiconductor chip and connected to said powerinput terminal for generating said internal voltage to be supplied tosaid first internal circuit based on said external voltage, and a firstreset signal generating circuit provided on said semiconductor chip forgenerating a first reset signal in response to said internal voltage toreset said first internal circuit or to keep circuit operation of saidfirst internal circuit halted until a first predetermined state isobtained, and a second reset signal generating circuit provided on saidsemiconductor chip for generating a second reset signal in response tosaid external voltage to reset said second internal circuit or to keepcircuit operation of said second internal circuit halted until a secondpredetermined state is obtained.
 2. A semiconductor device comprising:aninternal circuit provided on a semiconductor chip, a power inputterminal provided on said semiconductor chip for receiving an externalvoltage applied from outside said semiconductor chip, an internalvoltage generating circuit provided on said semiconductor chip andconnected to said power input terminal for generating an internalvoltage to be supplied to said internal circuit based on said externalvoltage, and a first reset signal generating circuit provided on saidsemiconductor chip for generating a first reset signal in response tosaid internal voltage to reset said internal circuit or to keep circuitoperation of said internal circuit halted until a predetermined state isobtained; a second reset signal generating circuit provided on saidsemiconductor chip for generating a second reset signal in response tosaid external voltage, said internal voltage generating circuit beingreset or circuit operation being kept halted until a predetermined stateis obtained with said second reset signal.
 3. The semiconductor deviceaccording to claim 2:wherein the cell plate potential of a memory cellformed on said semiconductor chip is applied in response to saidinternal voltage, and a substrate potential of said semiconductor chipis applied in response to said external voltage.
 4. A semiconductordevice comprising:an internal circuit provided on a semiconductor chip,a power input terminal provided on said semiconductor chip for receivingan external voltage applied from outside said semiconductor chip, afirst internal voltage generating circuit provided on said semiconductorchip and connected to said power input terminal for generating a firstinternal voltage to be supplied to said internal circuit based on saidexternal voltage, a first reset signal generating circuit provided onsaid semiconductor chip for generating a first reset signal in responseto said first internal voltage, a second internal voltage generatingcircuit provided on said semiconductor chip for generating a secondinternal voltage used in said internal circuit based on said firstinternal voltage supplied from said first internal voltage generatingcircuit, said second internal voltage generating circuit responsive tosaid first reset signal for being reset or kept halted until a firstpredetermined state is obtained, and a second reset signal generatingcircuit provided on said semiconductor chip for generating a secondreset signal in response to said second internal voltage to reset saidinternal circuit or keep circuit operation of said internal circuithalted until a second predetermined state is obtained.
 5. Asemiconductor device comprising:an internal circuit provided on asemiconductor chip, a power input terminal provided on saidsemiconductor chip for receiving an external voltage applied fromoutside said semiconductor chip, an internal voltage generating circuitprovided on said semiconductor chip and connected to said power inputterminal for generating an internal voltage to be supplied to saidinternal circuit based on said external voltage, a reset signalgenerating circuit provided on said semiconductor chip for generating,in response to said external voltage and said internal voltage, a resetsignal to reset said internal circuit or to keep circuit operation ofsaid internal circuit halted until a predetermined state is obtained,wherein said internal voltage is defined by first and second potentialsand said external voltage is defined by said second potential and athird potential, said reset signal generating circuit comprising:a firstinsulated-gate transistor having a control electrode to which said firstpotential is applied, a first current electrode to which said firstpotential is applied, and a second current electrode, a capacitor havinga first electrode to which said second potential is applied, and asecond electrode connected to said second current electrode of saidfirst insulated-gate transistor, a second insulated-gate transistorhaving a control electrode to which said third potential is applied, afirst current electrode to which said third potential is applied, and asecond current electrode, and having the same conductivity type as thatof said first insulated-gate transistor, a third insulated-gatetransistor having a first current electrode to which said secondpotential is applied, a control electrode connected to said secondcurrent electrode of said first insulated-gate transistor, and a secondcurrent electrode connected to said second current electrode of saidsecond insulated-gate transistor, and having the same conductivity typeas that of said first insulated-gate transistor, a first inverter havingan input terminal connected to said second current electrode of saidsecond insulated-gate transistor, and an output terminal, and a secondinverter having an input terminal connected to said output terminal ofsaid first inverter, and an output terminal for outputting said resetsignal.
 6. A semiconductor device comprising:an internal circuitprovided on a semiconductor chip, a power input terminal provided onsaid semiconductor chip for receiving an external voltage applied fromoutside said semiconductor chip, a first internal voltage generatingcircuit provided on said semiconductor chip and connected to said powerinput terminal for generating a first internal voltage to be supplied tosaid internal circuit based on said external voltage, a second internalvoltage generating circuit provided on said semiconductor chip andconnected to said power input terminal for generating a second internalvoltage to be supplied to said internal circuit based on said externalvoltage, and a reset signal generating circuit provided on saidsemiconductor chip for generating a reset signal in response to saidfirst and second internal voltages to reset said internal circuit or tokeep circuit operation of said internal circuit halted until apredetermined state is obtained;wherein said reset signal generatingcircuit is configured for generating said reset signal having the shapeof a pulse with rise and fall timings that are responsive, respectively,to said first and second internal voltages.
 7. The semiconductor deviceaccording to claim 6, wherein said first internal voltage is defined byfirst and second potentials and said second internal voltage is definedby said second potential and a third potential,said reset signalgenerating circuit comprising:a first insulated-gate transistor having acontrol electrode to which said first potential is applied, a firstcurrent electrode to which said first potential is applied, and a secondcurrent electrode, a capacitor having a first electrode to which saidsecond potential is applied, and a second electrode connected to saidsecond current electrode of said first insulated-gate transistor, asecond insulated-gate transistor having a control electrode to whichsaid third potential is applied, a first current electrode to which saidthird potential is applied, and a second current electrode, and havingthe same conductivity type as that of said first insulated-gatetransistor, a third insulated-gate transistor having a first currentelectrode to which said second potential is applied, a control electrodeconnected to said second current electrode of said first insulated-gatetransistor, and a second current electrode connected to said secondcurrent electrode of said second insulated-gate transistor, and havingthe same conductivity type as that of said first insulated-gatetransistor, a first inverter having an input terminal connected to saidsecond current electrode of said second insulated-gate transistor, andan output terminal, and a second inverter having an input terminalconnected to said output terminal of said first inverter, and an outputterminal for outputting said reset signal.
 8. A semiconductor devicecomprising:an internal circuit provided on a semiconductor chip, a powerinput terminal provided on said semiconductor chip for receiving anexternal voltage applied from outside said semiconductor chip, aninternal voltage generating circuit provided on said semiconductor chipand connected to said power input terminal for generating an internalvoltage to be supplied to said internal circuit based on said externalvoltage, and a first reset signal generating circuit provided on saidsemiconductor chip for generating a reset signal in response to saidinternal voltage to reset said internal circuit or to keep circuitoperation of said internal circuit halted until a predetermined state isobtained; wherein said first reset signal generating circuitcomprises:comparing means for comparing the voltages of twopredetermined nodes in said internal voltage generating circuit, andreset signal generating means for generating said reset signal inresponse to the results of comparison obtained by said comparing means.9. The semiconductor device according to claim 8, wherein said comparingmeans comprises:a first transistor of a first conductivity type having afirst current electrode connected to a first power potential point, acontrol electrode connected to a first input terminal, and a secondcurrent electrode, a second transistor of the first conductivity typehaving a control electrode connected to said first input terminal, afirst current electrode connected to said second current electrode ofsaid first transistor, and a second current electrode, a thirdtransistor of the first conductivity type having a first currentelectrode connected to said second current electrode of said firsttransistor, a control electrode connected to a second input terminal,and a second current electrode, a fourth transistor of a secondconductivity type having a first current electrode connected to a secondpower potential point, a control electrode, and a second currentelectrode connected to said second current electrode of said secondtransistor, a fifth transistor of the second conductivity type having afirst current electrode connected to said second power potential point,a control electrode connected to said second current electrode of saidfourth transistor, and a second current electrode connected to saidsecond current electrode of said third transistor, a sixth transistor ofthe second conductivity type having a first current electrode connectedto said control electrode of said fourth transistor, a second currentelectrode connected to said control electrode of said fifth transistor,and a control electrode, a seventh transistor of the second conductivitytype having a first current electrode connected to said controlelectrode of said fourth transistor, a second current electrodeconnected to said second current electrode of said third transistor, anda control electrode, a first inverter having an input terminal connectedto said second current electrode of said third transistor, and an outputterminal, a second inverter having an input terminal connected to saidoutput terminal of said first inverter, and an output terminal connectedto said control electrode of said sixth transistor, and a third inverterhaving an input terminal connected to said output terminal of saidsecond inverter, and an output terminal connected to said controlelectrode of said seventh transistor, wherein the results of comparisonare output from said output terminal of said second inverter.
 10. Asemiconductor device comprising:an internal circuit provided on asemiconductor chip, a power input terminal provided on saidsemiconductor chip for receiving an external voltage applied fromoutside said semiconductor chip, an internal voltage generating circuitprovided on said semiconductor chip and connected to said power inputterminal for generating an internal voltage to be supplied to saidinternal circuit based on said external voltage, and a reset signalgenerating circuit provided on said semiconductor chip for generating areset signal in response to said internal voltage to reset said internalcircuit or to keep circuit operation of said internal circuit halteduntil a predetermined state is obtained; wherein said internal voltageproduced by said internal voltage generating circuit is defined by firstand second potentials, said reset signal generating circuit comprising:afirst insulated-gate transistor having a control electrode to which saidfirst potential is applied, a first current electrode to which saidfirst potential is applied, and a second current electrode, a capacitorhaving a first electrode to which said second potential is applied, anda second electrode connected to said second current electrode of saidfirst insulated-gate transistor, a second insulated-gate transistorhaving a control electrode to which said first potential is applied, afirst current electrode to which said first potential is applied, and asecond current electrode, and having the same conductivity type as thatof said first insulated-gate transistor, a third insulated-gatetransistor having a first current electrode to which said secondpotential is applied, a control electrode connected to said secondcurrent electrode of said first insulated-gate transistor, and a secondcurrent electrode connected to said second current electrode of saidsecond insulated-gate transistor, and having the same conductivity typeas that of said first insulated-gate transistor, a first inverter havingan input terminal connected to said second current electrode of saidsecond insulated-gate transistor and an output terminal, and operatingwith said internal voltage, and a second inverter having an inputterminal connected to said output terminal of said first inverter and anoutput terminal for outputting said reset signal, and operating withsaid internal voltage.
 11. A semiconductor device comprising:an internalcircuit provided on a semiconductor chip, a power input terminalprovided on said semiconductor chip for receiving an external voltageapplied from outside said semiconductor chip, internal voltagegenerating circuitry provided on said semiconductor chip and connectedto said power input terminal for generating an internal voltage to besupplied to said internal circuit based on said external voltage, and areset signal generating circuit provided on said semiconductor chip forgenerating a reset signal in response to a reference level of saidinternal voltage to reset said internal circuit or to keep circuitoperation of said internal circuit halted until a predetermined state isobtained; wherein said internal voltage generating circuitry comprises:areference voltage generating circuit for generating a reference voltagerepresenting said reference level of said internal voltage, and saidreset signal generating circuit comprises:a driver for detecting thatthe potential of a predetermined node of said reference voltagegenerating circuit reaches a predetermined potential, and a reset signalgenerating unit for generating said reset signal in response to theoutput signal of said driver.
 12. The semiconductor device according toclaim 11, wherein said external voltage is defined by first and secondpotentials,said driver comprises:a first insulated-gate transistorhaving a gate connected to said predetermined node, a source to whichsaid first potential is applied, and a drain, and resistor means havinga first end connected to said drain of said first insulated-gatetransistor, and a second end to which said second potential is applied,and said reset signal generating unit comprises:a first inverter havingan input terminal connected to said first end of said resistor means andan output terminal for inverting and outputting a signal sent from saidinput terminal, and operating by said external voltage, a secondinsulated-gate transistor having a source to which said second potentialis applied, a gate connected to said first end of said resistor means,and a drain, a third insulated-gate transistor having a source to whichsaid second potential is applied, a gate connected to said outputterminal of said first inverter, and a drain, a fourth insulated-gatetransistor having a drain connected to said drain of said secondinsulated-gate transistor, a gate connected to said drain of said thirdinsulated-gate transistor, and a source to which said first potential isapplied, a fifth insulated-gate transistor having a gate connected tosaid drain of said fourth insulated-gate transistor, a source to whichsaid first potential is applied, and a drain connected to said gate ofsaid fourth insulated-gate transistor, and a second inverter having aninput terminal connected to said drain of said fifth insulated-gatetransistor, and an output terminal for outputting said reset signal.